The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating an output enable signal in response to a read command and CAS latency information and a method for generating an output enable signal.
In general, a semiconductor memory device such a Double Data Rate Synchronous DRAM (DDR SDRAM) receives a read command synchronized with an external clock signal during a read operation and outputs data synchronized with an internal clock signal to an external device. That is, a semiconductor memory device uses an internal clock signal to output data instead of an external clock signal. Therefore, a semiconductor memory device needs synchronizing a read command, which is synchronized with an external clock signal, to an internal clock signal in order to perform a read operation. In view of a read command, a synchronized clock signal is changed from an external clock signal to an internal clock signal. It is referred to as domain crossing.
A semiconductor memory device includes various circuits for performing domain crossing. For example, a semiconductor memory device includes an output enable signal generating circuit for performing domain crossing. The output enable signal generating circuit synchronizes a read command, which is synchronized with an external clock signal, to an internal clock signal and outputs the read command as an output enable signal. After completely performing domain crossing, the output enable signal includes CAS latency information. A semiconductor memory device uses such an output enable signal to output data at a desired time with being synchronized to an external clock signal after receiving a read command.
For reference, the CAS latency includes information on time duration from a time of applying a read command to a time of outputting desired data in one cycle of an external clock signal as a unit time. The CAS latency information is generally stored in a mode register set (MRS) in a semiconductor memory device.
A skew is generated between an external clock signal and an internal clock signal due to delay elements in a semiconductor memory device. In order to compensate the skew, a semiconductor memory device includes an internal clock signal generating circuit. The internal clock signal generating circuit includes a phase locked loop circuit and a delay locked loop circuit. A DLL clock generated from a delay locked loop circuit is exemplarily described as an internal clock signal.
FIG. 1 is a block diagram illustrating an output enable signal generating circuit of a semiconductor memory device.
Referring to FIG. 1, the output enable signal generating circuit includes a reset signal synchronizer 110, an initialize 120, a DLL clock counter 130, an OE delay replica model 140, an external clock counter 150, a latch unit 160, and a comparator 170.
Hereinafter, an operation of an output enable signal generating circuit will be described.
The DLL clock counter 130 and the external clock counter 150 DLL are reset by a clock counter reset signal RST_DLL and an external clock counter reset signal RST_EXT in response to an output enable reset signal RST_OE. The DLL clock counter 130 counts a DLL clock signal CLK_DLL and the external clock counter 150 counts an external clock signal CLK_EXT. The DLL clock counter 130 performs a counting operation from an initial counting value which is setup by the initialize 120 corresponding to CAS latency.
When a read signal RD is activated in response to a read command and applied, the latch unit 160 latches an external clock counting value CNT_EXT<0:2> counted by the external clock counter 150 and outputs the latched counting value CNT_LAT<0:2>. The comparator 170 compares a DLL clock counting value CNT_DLL<0:2> from the DLL clock counter 130 and the latched counting value CNT_LAT<0:2> and activates an output enable signal OE when the DLL clock counting value CNT_DLL<0:2> becomes identical to the latched counting value CNT_LAT<0:2>.
The output enable signal OE is a signal synchronized with the DLL clock signal CLK_DLL and includes CAS latency (CL) information. The semiconductor memory device uses the output enable signal OE to output data.
The output enable signal generating circuit is reset at a DLL reset mode, at a power down mode, and when CAS latency (CL) stored in an MRS is changed. In these states, domain crossing of an external clock signal CLK_EXT and a DLL clock signal CLK_DLL cannot be smoothly performed. Therefore, the DLL clock counter 130 and the external clock counter 150 are reset in response to an output enable reset signal RST_OE. The output enable reset signal RST_OE is a pulse signal synchronized with a DLL clock signal CLK_DLL or an external clock signal CLK_EXT after delayed based on a corresponding state. That is, the output enable reset signal RST_OE may have a domain corresponding to a DLL clock signal CLK_DLL or a domain corresponding to an external clock signal CLK_EXT.
The reset signal synchronizer 110 includes a flip-flop for synchronizing an output enable reset signal RST_OE to a DLL clock signal CLK_DLL. An activation edge of a DLL clock signal CLK_DLL input to the flip-flop may become close to an activation edge of an output enable reset signal RST_OE. In this case, a synchronizing operation cannot be performed because it is impossible to sufficiently secure a setup/hold time. Such a problem becomes more serious according to a process, a voltage, and a temperature (PVT). In order to prevent this problem, the reset signal synchronizer 110 includes a plurality of flip-flops arranged in cascade.
FIG. 2 is a block diagram illustrating a reset signal synchronizer 110 of FIG. 1.
Referring to FIG. 2, the reset signal synchronizer 110 includes a plurality of flip-flops and each of the flip-flops receives a DLL clock signal CLK_DLL. An output enable reset signal RST_OE is synchronized with a DLL clock signal CLK_DLL through the flip-flops. Finally, the DLL clock counter reset signal RST_DLL is output with synchronized to the DLL clock signal CLK_DLL.
However, the reset signal synchronizer 110 having a plurality of flip-flops in cascade cause another problem. The reset signal synchronizer 110 having a plurality of flip-flops may reduce an error generation rate because a setup/hold time of activation edges of a DLL clock signal CLK_DLL and an output enable reset signal RST_OE can be secured as the number of flip-flops increases. However, if a frequency of a DLL clock signal CLK_DLL increases, the error generation rate increases again due to the setup/hold time. It is expected that such an error generation rate increases continuously because an operation speed of a semiconductor memory device increases gradually.
As the reset signal synchronizer 110 includes more flip-flops, a circuit area also increases in proportion to the increased number of flip-flops and an activation time of a DLL clock counter reset signal RST_DLL becomes gradually slow. If an activation time of a DLL clock counter reset signal RST_DLL becomes slow, a time of counting operation in the DLL clock counter 130 and the external clock counter 150 become also slow. It means that a time of receiving a read signal RD and a time of activating an output enable signal OE also become slow. Finally, it slows down an operation speed of a semiconductor memory device.